[AKD4955-A] 2011/08 - 1 - general description the AKD4955-A is an evaluation board for ak4955, 24b it stereo codec with a microphone/ speaker/ video amplifiers, dsp and ldo. the AKD4955-A has the digital audio i/f and can achieve the interface with digital audio systems via optical connector. ? ordering guide AKD4955-A --- ak4955 evaluation board (cable for connecting with usb port of pc and control software are packed with this.) function ? dir/dit with optical input/output ? bnc connector for an external clock input port3 (dsp) lin ri n lout rout ak4118a (dit/dir) av d d vout vin spp spn lin1 rin1 lin2 rin2 ak4955 mini jack ai n mini jack ldo ( t1 ) usb pic4550 +5v ldo (t2) 3.3v 5v lvdd svdd dvdd 3.3v 5v 1.8v 5v external clock ldo (t3) opt in opt out port4 (10pin-ct rl) for tvdd min figure 1.AKD4955-A block diagram ak4955 evaluation board rev.3 AKD4955-A
[AKD4955-A] 2011/08 - 2 - ? operation sequence 1) set up the power supply lines. 2) setup the audio i/f evaluation mode. (1) evaluation of a/d using dit of ak4118a. (1-1) setting with external slave mode. (1-2) setting with external master mode. (2) evaluation of d/a using dir of ak4118a. (2-1) setting with external slave mode. < default > (2-2) setting with external master mode. (3) evaluation of a/d, d/a using port3 (dsp). (3-1) setting with external slave mode. (3-2) setting with external master mode. (3-3) setting with pll slave mode. (3-4) setting with pll master mode. (4) evaluation of external loop-back (a/d -> d/a). (4-1) setting with external slave mode. (4-2) setting with external master mode. (4-3) setting with pll slave mode. (4-4) setting with pll master mode. 3) jumper pins and sw setting. (1) setting of other jumper pins. (2) setting of sw. 4) power on.
[AKD4955-A] 2011/08 - 3 - 1) set up the power supply lines. (1-1) in case of using the regulator. < default > jp20 av dd- se l a vdd reg jp2 3 lv dd- sel lv d d reg jp25 svdd-sel svdd reg jp26 d3v-sel d3v reg jp21 dvdd-sel dvdd reg jp24 lvc-sel lv c reg figure 2.setting of jumper pins, when using the regulator. name of jack color default setting using +5v red 5v for regulator. avdd green open for avdd of ak4955 lvdd green open for lvdd of ak4955 svdd green open for svdd of ak4955 d3v green open for ak4118a and digital logic. dvdd green open for dvdd of ak4955 lvc green open for tvdd of ak4955 and digital logic. agnd black 0v for analog ground dgnd black 0v for digital ground table 1.set up of power supply lines (1-2) in case of using the power supply connectors. jp20 av dd- se l a vdd reg jp2 3 lv dd- sel lv d d reg jp25 svdd-sel svdd reg jp26 d3v-sel d3v reg jp21 dvdd-sel dvdd reg jp24 lvc-sel lv c reg figure 3.setting of jumper pins, when using the power supply connectors. name of jack color default setting using +5v red open for regulator. avdd green +2.8v ~ +3.6v [typ:+3.3v] for avdd of ak4955 lvdd green +2.7v ~ +5.5v [typ:+3.3v] for lvdd of ak4955 svdd green +2.7v ~ +5.5v [typ:+3.3v] for svdd of ak4955 d3v green +2.7v ~ +3.6v [typ:+3.3v] for ak4118a and digital logic. dvdd green +1.6v ~ +2.0v [typ:+1.8v] for dvdd of ak4955 lvc green +1.6v ~ +3.6v [typ:+1.8v] for tvdd of ak4955 and digital logic. agnd black 0v for analog ground dgnd black 0v for digital ground table 2.set up of power supply lines ( note 1 ) note 1.each supply line should be distributed from the power supply unit.
[AKD4955-A] 2011/08 - 4 - 2) setup the audio i/f evaluation mode. in case of using the ak4118a when evaluating the ak4955, both the ak4955 and ak4118a?s audio interface formats must be matched. refer to the datasheet for ak4955?s audio interface format, and ak 4118a?s audio interface format ( table 4 ). the ak4118a operates at sampling frequency of 32 khz or more. if the sampling frequency is slower than 32 khz, please use other mode. in addition, mclk of ak4118a suppor ts 256fs and 512fs. when evaluating in a condition except above, please use other mode. refer to the datasheet for register setting of the ak4955. (1) evaluation of a/d using dit of ak4118a. (1-1) setting with external slave mode x1 (x?tal) and port2 (totx) are used. nothing should be connected to port1 (torx) and port3 (dsp). mcki, bick and lrck are supplied from the ak4118a, and sdto of the ak4955 is output to the ak4118a. in addition, registers of the ak4955 should be set to ?external slave mode? and setting of ak4118a should be set to ?master mode?. sw4 (m/s) should be set to ?on (h)?. jp10 xti-sel jp11 bick-sel 2 3 4 xtl mcko 4 8 5 10pin dir 4040-32f s 4040-64f s jp13 lrck-sel 5 62 10pin dir 4040 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ext 10 p in figure 4.setting of jumper pins with external slave mode (1-2) setting with external master mode x1 (x?tal) and port2 (totx) are used. nothing should be connected to port1 (torx) and port3 (dsp). mcki is supplied from the ak4118a, and bick, lrck and sdto of the ak4955 is output to the ak4118a. in addition, registers of the ak4955 should be se t to ?external master mode? and setting of ak4118a should be set to ?slave mode?. sw4 (m/s) should be set to ?off (l)?. jp10 xti-sel jp11 bick-sel 2 3 4 xtl mcko 4 8 5 10pin dir 4040-32f s 4040-64f s jp13 lrck-sel 5 62 10pin dir 4040 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ext 10 p in figure 5.setting of jumper pins with external master mode
[AKD4955-A] 2011/08 - 5 - (2) evaluation of d/a using dir of ak4118a. (2-1) setting with external slave mode < default > port1 (torx) is used. nothing should be connected to port2 (totx) and port3 (dsp). mcki, bick, lrck and sdti are supplied from the ak4118a. in addition, registers of the ak4955 should be set to ?external slave mode? and setting of ak4118a should be set to ?master mode?. sw4 (m/s) should be set to ?on (h)?. jp10 xti-sel jp11 bick-sel 2 3 4 xtl mcko 4 8 5 10pin dir 4040-32f s 4040-64f s jp13 lr ck-sel 5 62 10pin dir 4040 th r in v jp12 bick-phase jp16 mcki-sel 4 8 5 dir gnd ex t 10pin jp1 5 sdti-sel 5 62 dir adc 10 p in figure 6.setting of jumper pins with external slave mode (2-2) setting with external master mode port1 (torx) is used. nothing should be connected to port2 (totx) and port3 (dsp). mcki and sdti are supplied from the ak4118a, and bick and lrck of the ak4955 is output to the ak4118a. in addition, registers of the ak4955 should be se t to ?external master mode? and setting of ak4118a should be set to ?slave mode?. sw4 (m/s) should be set to ?off (l)?. jp10 xti-sel jp11 bick-sel 2 3 4 xtl mcko 4 8 5 10pin dir 4040-32f s 4040-64f s jp13 lr ck-sel 5 62 10pin dir 4040 th r in v jp12 bick-phase jp16 mcki-sel 4 8 5 dir gnd ex t 10pin jp1 5 sdti-sel 5 62 dir adc 10 p in figure 7.setting of jumper pins with external master mode
[AKD4955-A] 2011/08 - 6 - (3) evaluation of a/d, d/a using port3 (dsp). (3-1) setting with external slave mode registers of the ak4955 should be set to ?external slave mode?. sw4 (m/s) should be set to ?on (h)?. ak4955 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs mc lk 256fs, 512fs or 1024fs figure 8.external slave mode port3 (dsp) is used. nothing should be connected to port1 (torx) and port2 (totx). mclk, bick, lrck, and sdti are input from port3 (dsp) and sdto of the ak4955 is output to the port3 (dsp). jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 6 2 10 p in di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ex t 10pin jp15 sdti-sel 5 62 dir adc 10 p in jp1 figure 9.setting of jumper pins with external slave mode ( note 2 ) note 2.jp12 (bick-phase) is jumper which decides polarity of bi ck, ?thr? or ?inv? should be selected according to the audio i/f format.
[AKD4955-A] 2011/08 - 7 - (3-2) setting with external master mode registers of the ak4955 should be set to ?external master mode?. sw4 (m/s) should be set to ?off (l)?. ak4955 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs mc lk 256fs, 512fs or 1024fs figure 10.external master mode port3 (dsp) is used. nothing should be connected to port1 (torx) and port2 (totx). mclk and sdti are input from port3 (dsp) and bick, lrck and sdto of the ak4955 is output to the port3 (dsp). jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 6 2 10 p in di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ex t 10pin jp15 sdti-sel 5 62 dir adc 10 p in jp1 figure 11.setting of jumper pins with external master mode
[AKD4955-A] 2011/08 - 8 - (3-3) setting with pll slave mode a reference clock of pll is selected among the input clocks supplied to mcki pin. the required clock to the ak4955 is generated by an internal pll circuit. sw4 (m/s) should be set to ?on (h)?. (a) pll reference clock: mcki pin registers of the ak4955 should be set to ?p ll slave mode? (reference clock: mcki pin). bick and lrck inputs should be synchronized with mcko output. however the phase between mcko and lrck dose not matter. ak4955 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1f s 32fs 11.2896mhz, 12mhz, 13.5mhz 24mhz, 25mhz, 27mhz mclk 256fs/128fs/64fs/32fs figure 12.pll slave mode 1 (pll reference clock: mcki pin) j10 (ext) and port3 (dsp) are used ( note 3 ). nothing should be connected to port1 (torx) and port2 (totx). mcki is input from j10 (ext). bick, lrck and sdti are input from port3 (dsp). mcko and sdto of the ak4955 is output to the port3 (dsp). jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 62 10 p in di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 8 5 dir gnd ex t 10pin jp1 5 sdti-sel 5 62 dir adc 10pin jp1 jp18 ext figure 13.setting of jumper pins with pll slave mode ( note 4 ) note 3.when a termination (51 ? ) of j10 (ext) is not used, jp18 (ext) should be open. note 4.jp12 (bick-phase) is jumper which decides polarity of bi ck, ?thr? or ?inv? should be selected according to the audio i/f format.
[AKD4955-A] 2011/08 - 9 - (b) pll reference clock: bick pin registers of the ak4955 should be set to ?p ll slave mode? (reference clock: bick pin). ak4955 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs, 64fs figure 14.pll slave mode 2 (pll reference clock: bick pin) port3 (dsp) is used. nothing should be connected to port1 (torx) and port2 (totx). bick, lrck and sdti are input from port3 (dsp). sdto of the ak4955 is output to the port3 (dsp). jp11 bick-sel 4 85 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 62 10 p in di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 8 5 dir gnd ext 10pin jp15 sdti-sel 5 6 2 dir adc 10 p in figure 15.setting of jumper pins with pll slave mode ( note 5 ) note 5.jp12 (bick-phase) is jumper which decides polarity of bick, ?thr? or ?inv? should be selected according to the audio i/f format.
[AKD4955-A] 2011/08 - 10 - (3-4) setting with pll master mode the master clock is input from mcki pin of j10 (ext ). an internal pll circuit generates mcko, bick, and lrck. in addition, registers of the ak4955 sh ould be set to ?pll master mode?. sw4 (m/s) should be set to ?on (h)?. ak4955 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1f s 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 13.5mhz 24mhz, 25mhz, 27mhz mclk figure 16.pll master mode j10 (ext) and port3 (dsp) are used ( note 6 ). nothing should be connected to port1 (torx) and port2 (totx). mcki is input from j10 (ext) and sdti is input from port3 (dsp). bick, lrck, mcko and sdto of the ak4955 are output to the port3 (dsp). jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 62 10 p in di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 8 5 dir gnd ex t 10pin jp1 5 sdti-sel 5 62 dir adc 10pin jp1 jp18 ext figure 17.setting of jumper pins with pll slave mode note 6.when a termination (51 ? ) of j10 (ext) is not used, jp18 (ext) should be open.
[AKD4955-A] 2011/08 - 11 - (4) evaluation of external loop-back (a/d -> d/a). (4-1) setting with external slave mode. j10 (ext) is used ( note 7 ). nothing should be connected to port1 (torx), port2 (totx) and port3 (dsp). mcki is input from j10 (ext). bick and lrck are generated by on-board divider. sdti is connected to sdto of the ak4955 as loopback. in addition, registers of the ak4955 shou ld be set to ?external slave mode?. sw4 (m/s) should be set to ?on (h)?. jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 62 10pin di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ext 10pin jp15 sdti-sel 5 6 2 dir adc 10 p in jp17 4040-sel jp1 8 ext mcki mcko figure 18.setting of jumper pins with external slave mode ( note 8 , note 9 ) note 7.when a termination (51 ? ) of j10 (ext) is not used, jp18 (ext) should be open. note 8.jp12 (bick-phase) is jumper which decides polarity of bick, ?thr? or ?inv? should be selected according to the audio i/f format. note 9.when bick of 32fs is used, jp11 (bick-sel) should be set to ?4040-32fs? side. (4-2) setting with external master mode. j10 (ext) is used ( note 10 ). nothing should be connected to port1 (torx), port2 (totx) and port3 (dsp). mcki is input from j10 (ext), sdti is connected to sdto of the ak4955 as loopback. in addition, registers of the ak4955 shou ld be set to ?external master mode?. sw4 (m/s) should be set to ?off (l)?. jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 62 10pin di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ext 10pin jp15 sdti-sel 5 6 2 dir adc 10 p in jp17 4040-sel jp1 8 ext mcki mcko figure 19.setting of jumper pins with external master mode note 10.when a termination (51 ? ) of j10 (ext) is not used, jp18 (ext) should be open.
[AKD4955-A] 2011/08 - 12 - (4-3) setting with pll slave mode. sw4 (m/s) should be set to ?on (h)?. (a) pll reference clock: mcki pin j10 (ext) is used ( note 11 ). nothing should be connected to port1 (torx), port2 (totx) and port3 (dsp). mcki is input from j10 (ext). bick and lrck are generated by using on-board divider and mcko of the ak4955. sdti is connected to sdto of the ak4955 as loopback. in addition, registers of the ak4955 should be set to ?pll slave mode? (reference clock: mcki pin). jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 62 10pin di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ext 10pin jp15 sdti-sel 5 6 2 dir adc 10 p in jp17 4040-sel jp18 ext mcki mcko figure 20.setting of jumper pins with pll slave mode ( note 12 , note 13 ) note 11.when a termination (51 ? ) of j10 (ext) is not used, jp18 (ext) should be open. note 12.jp12 (bick-phase) is jumper which decides polarity of bick, ?thr? or ?inv? should be selected according to the audio i/f format. note 13.when bick of 32fs is used, jp11 (bick-sel) should be set to ?4040-32fs? side. (b) pll reference clock: bick pin port3 (dsp) is used. nothing should be connected to port1 (torx), port2 (totx) and j10 (ext). bick and lrck are generated by on-board divider which used mclk from port3 (dsp). sdti is connected to sdto of the ak4955 as loopback. in addition, registers of the ak4955 should be set to ?pll slave mode? (reference clock: bicki pin). jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 6 2 10 p in di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gn d ex t 10pin jp15 sdti-sel 5 62 dir adc 10 p in jp17 4040-sel mcki mc ko jp14 mckio mcki mck o figure 21.setting of jumper pins with pll slave mode ( note 14 , note 15 ) note 14.jp12 (bick-phase) is jumper which decides polarity of bick, ?thr? or ?inv? should be selected according to the audio i/f format. note 15.when bick of 32fs is used, jp11(bick-sel) should be set to ?4040-32fs? side.
[AKD4955-A] 2011/08 - 13 - (4-4) setting with pll master mode. j10 (ext) is used ( note 16 ). nothing should be connected to port1 (torx), port2 (totx) and port3 (dsp). mcki is input from j10 (ext), sdti is connected to sdto of the ak4955 as loopback. sw4 (m/s) should be set to ?off (l)?. jp11 bick-sel 4 8 5 10 p in dir 4040-32fs 4040-64fs jp13 lrck-sel 5 62 10pin di r 404 0 th r in v jp12 bick-phase jp16 mcki-sel 4 85 dir gnd ext 10pin jp15 sdti-sel 5 6 2 dir adc 10 p in jp17 4040-sel jp1 8 ext mcki mcko figure 22.setting of jumper pins with pll master mode note 16.when a termination (51 ? ) of j10 (ext) is not used, jp18 (ext) should be open.
[AKD4955-A] 2011/08 - 14 - 3) jumper pins and sw setting. (1) setting of other jumper pins. [jp6 (lin-sel)]: the selection of input signal to lin1 pin and lin2 pin. l1-mini : input signal of lin1 pin is supplied from j1 (ain). < default > l1-bnc : input signal of lin1 pin is supplied from j3 (lin). l2-mini : input signal of lin2 pin is supplied from j1 (ain). l2-bnc : input signal of lin2 pin is supplied from j3 (lin). < default > [jp7 (rin-sel)]: the selection of input signal to rin1 pin and rin2 pin. r1-mini : input signal of rin1 pin is supplied from j1 (ain). < default > r1-bnc : input signal of rin1 pin is supplied from j5 (rin). r2-mini : input signal of rin2 pin is supplied from j1 (ain). r2-bnc : input signal of rin2 pin is supplied from j5 (rin). < default > [jp8 (min-sel)]: the selection of input mode of min pin. ext : ?external resistance mode?. int : ?internal resistance mode?. < default > [jp9 (spk-gnd)]: the selec tion of condition for gnd of j9 (spk-out) connector. short : connect to gnd. < default > open : none connect to gnd. [jp19 (gnd)]: analog ground and digital ground short : common. (the connector ?dgnd? can be open.) < default > open : separated. [jp28 (ctrl-sel)]: the selection of serial control i/f. usb : use u10 (usb) connector. < default > 10pin : use port4 (10pin-ctrl). [jp29 (pic)]: not to use. [jp100 (mpwr-sel)] the selection of mic-power. open : mic-power is not supplied. < default > short : mic-power is supplied. [jp101 (rin1-sel)] the selection of input signal to rin1 pin. rin1 : connect to analog signal from jp7 (rin-sel). < default > dmclk : connect to digital microphone clock supply input. [jp102 (lin1-sel)] the selection of input signal to lin1 pin. lin1 : connect to analog signal from jp6 (lin-sel). < default > dmdat : connect to digital microphone data input. [jp103 (cdtio/cad0)] the selection of input signal to cdtio/cad0 pin. cdtio : when i2c pin = ?l?, cdtio is selected. < default > cad0 : when i2c pin = ?h?, cad0 is selected. [jp104 (csn/sda)] the selection of input signal to csn/sda pin. csn : when i2c pin = ?l?, csn is selected. < default > sda : when i2c pin = ?h?, sda is selected.
[AKD4955-A] 2011/08 - 15 - (2) setting of sw. upper-side is ?on(h)? and lower-side is ?off(l)?. [sw1] (sw dip-4): mode setting for ak4118a. no. name on (?h?) off (?l?) default 1 dif2 on 2 dif1 off 3 dif0 see table 4 off 4 ocks1 see table 5 off table 3.mode setting for ak4118a lrck bick mode dif2 dif1 dif0 daux sdto i/o i/o 0 l l l 24bit, left justified 16bit, right justified h/l o 64fs o 1 l l h 24bit, left justified 18bit, right justified h/l o 64fs o 2 l h l 24bit, left justified 20bit, right justified h/l o 64fs o 3 l h h 24bit, left justified 24bit, right justified h/l o 64fs o 4 h l l 24bit, left justified 24bit, left justified h/l o 64fs o default 5 h l h 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 h h l 24bit, left justified 24bit, left justified h/l i 64 -128fs i 7 h h h 24bit, i 2 s 24bit, i 2 s l/h i 64 -128fs i table 4.audio i/f format setting for ak4118a ocks1 mcko1 l 256fs default h 512fs table 5.master clock setting for ak4118a [sw4] (sw dip-3): mode setting for ak4955. no. name on (?h?) off (?l?) default 1 i2c i 2 c bus 3-wire serial off 2 cad0 cad0 pin = ?1? cad0 pin = ?0? off 3 m/s when the ak4955 is in ?slave mode?. when the ak4955 is in ?master mode?. on table 6.mode setting for ak4955
[AKD4955-A] 2011/08 - 16 - 4) power on. upper-side is ?h? and lower-side is ?l?. [sw2] (dio-pdn) : resets the ak4118a. keep ?h? during normal operation. the ak4118a should be resets once bringing ?l? upon power-up. [sw3] (pdn) : resets the ak4955. keep ?h? during normal operation. the ak4955 should be resets once bringing ?l? upon power-up. ? indication for led [led1] (int0) : monitor int0 pin of the ak4118a. led turns on when some error has occurred to ak4118a. ? control port it is possible to control AKD4955-A via general usb port. connect cable with the u10 (usb) on board and pc. control software is packed with this board. the software operation sequence is included in the evaluation board manual.
[AKD4955-A] 2011/08 - 17 - analog input / output circuits 1) input circuit (1-1) mic/line1, 2 input circuit (except for digital-mic circuit). l2-bnc rin2 lin1 rin1 lin2 mpwr- sel jp100 2.2k 2.2k 2.2k 2.2k r1- mini r1- bnc l2-mini r2- mini r2- bnc j5 rin 1 2 3 4 5 j1 ain 5 2 1 j3 lin 1 2 3 4 5 mpwr lin2 lin1 rin1 rin2 mpwr 1u 1u 1u 1u jp6 lin-sel jp7 rin- sel min i- l c h bnc-lch min i- rc h bnc-rch l1-mini l1-bnc figure 23.circuit diagram of mic/lin1, 2 input the mic/line1, 2 inputs are sh ared with j1, j3 and j5. please select the input to be used w ith jp6 (lin-sel) and jp7 (rin-sel). (1-2) video input circuit. 0.1u vin j2 vin 1 2 3 4 5 75 figure 24.circuit diagram of video input (1-3) monaural input circuit. min 33k j8 min 1 2 3 4 5 + 1u jp8 min- sel 33k ext int min figure 25.circuit diagram of monaural input
[AKD4955-A] 2011/08 - 18 - 2) output circuit (2-1) line output circuit. lout rout + 1u + 1u 20k 20k 220 220 j6 lout 1 2 3 4 5 j7 rout 1 2 3 4 5 figure 26.circuit diagram of line output (2-2) video output circuit. j4 vout 1 2 3 4 5 75 vout figure 27.circuit diagram of video output (2-3) speaker output circuit. 16 j9 spk-out 5 2 1 spp spn jp9 spk-gnd 16 (open) (open) figure 28.circuit diagram of speaker output
[AKD4955-A] 2011/08 - 19 - control soft manual evaluation board and control soft settings 1. set an evaluation board properly. 2. connect a pc and an evaluation board. 3. the usb control is recognized as hid (human interface device) on the pc. it is not necessary to install a new driver. 4. start up the control program. ( note 17 ) note 17. the ak4955 should be reset by the pdn pin after the power supplies are applied. after that, ?dummy comman d? should be executed. 5. proceed evaluation by followi ng the process below. figure 29.window of control soft
[AKD4955-A] 2011/08 - 20 - operation overview function, register map and testing tool can be controlled by this control soft. these controls are selected by upper tabs. buttons which are frequently used such as register initia lizing button ?write default?, are located outside of the switching tab window. refer to the ? dialog boxes? for details of each dialog box setting. 1. [port reset]: click this button after the control soft starts up. 2. [write default]: initializes registers when the device is reset by a hardware reset, use this button to initialize the registers. 3. [all write]: executes write commands for all registers displayed. 4. [all read]: executes read commands for all registers displayed. 5. [save]: saves current register settings to a file. 6. [load]: executes data write from a saved file. 7. [all req write]: opens ?all req write? dialog box. 8. [data r/w]: opens ?data r/w? dialog box 9. [sequence]: opens ?sequence? dialog box. 10. [sequence(file)]: opens ?sequence(file)? dialog box. 11. [read]: reads current register settings and displays on to the register area (on the right of the main window). this is different from [all read] button, it does not reflect to a register map, only displaying register settings in hexadecimal. 12. [read:disable/enable]: the register setting of [read]. read: read function enable. 0: disable < default > 1: enable 13. [dummy command]: the dummy command is written ( note 18 ). note 18. the ak4955 should be reset by the pdn pin after the power supplies are applied. after that, ?dummy comman d? should be executed.
[AKD4955-A] 2011/08 - 21 - tab functions 1. [function]: function control this tab is for function. each operation is executed by [function] buttons on the left side of the screen ( note 19 , note 20 ). note 19. please refer to the following settin g when you use the ?function? function. mode= ?external slave mode?, fs= ?7.35khz 48khz?, audio i/f format= ?24bit msb justified? note 20. the ak4955 should be reset by the pdn pin after the power supplies are applied. after that, ?dummy comman d? should be executed. figure 30.window of [function]
[AKD4955-A] 2011/08 - 22 - 2. [reg]: register map this tab is for a register writing and reading. each bit on the register map is a push-button switch. button down indicates ?h? or ?1? and the bit name is in red (when read only it is in deep red). button up indicates ?l? or ?0? and the bit name is in blue (when read only it is in gray). gray-out registers are read only registers. they can not be controlled. the registers which is not defined in the datasheet are indicated as ?---?. figure 31.window of [reg]
[AKD4955-A] 2011/08 - 23 - 2-1. [write]: data writing dialog it is for when changing two or more bits on the same address at the same time. click [write] button located on the right of the eac h corresponded address fo r a pop-up dialog box. when the checkbox is checked, the data will be ?h? or ?1?. when the checkbox is not checked, the data will be ?l? or ?0?. click [ok] to write setting values to th e registers, or click [cancel] to cancel this setting. figure 32.window of [register set] 2-2. [read]: data read click [read] button located on the ri ght of the each corresponded addr ess to execute a register read. after register reading, the display will be updated regarding to the register status. button down indicates ?h? or ?1? and the bit name is in red (when read only it is in deep red). button up indicates ?l? or ?0? and the bit name is in blue (when read only it is in gray). please be aware that button statuses will be changed by a read command.
[AKD4955-A] 2011/08 - 24 - 3. [tool]: testing tools evaluation testing tools are available in this tab. click buttons for each testing tool. figure 33.window of [tool]
[AKD4955-A] 2011/08 - 25 - 3-1. [repeat test]: repeat test dialog click [repeat test] button in the test tab to open a repeat test dialog shown below. repeat writing test can be executed by this dialog. figure 34.window of [repeat test] [start] button : starts the repeat test. a dialog for saving a file of the test result will open when clicking this button. name the file. test will start after specifying a saving file. [close] button : closes this dialog and finishes the process. [address] box : data writing address in hexadecimal numbers. [start data] box : start data in hexadecimal numbers. [end data] box : end data in hexadecimal numbers. [step] box : data write step interval. [repeat count] box : repeat count of the test writing. [up and down] box : data write flow is changed as below. ? checked : writes in step interval from the start data to the end data and turn back from the end data to the start data. [example] start data = 00, end data = 05, step = 1, [ ]?for 1 count. data flow : [00 01 02 03 04 05 05 04 03 02 01 00] x repeat count number ? not checked : writes in step interval from the st art data to the end data and finishes writing. [example] start data = 00, end data = 05, step = 1, [ ]?for 1 count. data flow : [00 01 02 03 04 05] x repeat count number [sampling frequency] box : selects sampling frequency 44.1 khz/48 khz [count] box : indicates the count number during a repeat test. [lch level] box : indicates th e lch level during a repeat test.
[AKD4955-A] 2011/08 - 26 - 3-2. [loop setting]: loop dialog click [loop setting] button in the tool tab to open loop setting dialog as shown below. writing test can be executed. figure 35.window of [loop] [ok] button : starts the test. [cancel] button : closes the dialog and finishes the process. [address] box : data writing address in hexadecimal numbers. [start data] box : start data in hexadecimal numbers. [end data] box : end data in hexadecimal numbers. [interval] box : data write interval time. [step] box : data write step interval. [mode select] box : mode select check box. ? checked : writes in step interval from the start data to the end data and turn back from the end data to the start data. [example] start data = 00, end data = 05, step = 1 data flow : 00 01 02 03 04 05 05 04 03 02 01 00 ? not checked : writes in step interval from the start data to the end data and finishes writing. [example] start data = 00, end data = 05, step = 1 data flow : 00 01 02 03 04 05
[AKD4955-A] 2011/08 - 27 - dialog boxes 1. [all req write]: all reg write dialog box click [all reg write] button in the main window to open register setting files. register setting files saved by [save] button can be applied. figure 36.window of [all reg write] [open (left)] : selects a register setting file (*.akr). [write] : executes register wr iting by the setting of selected file. [write all] : executes all register writings. selected files are executed in descending order. [help] : opens a help window. [save] : saves a register setting file assignment. the file name is ?*.mar?. [open (right)] : opens a saved register setting file assignment ?*. mar?. [close] : closes the dialog box and finish the process. ~ operating suggestions ~ 1. those files saved by [save] button and opened by [open] button on the right of the dialog ?*.mar? should be stored in the same folder. 2. when register settings are changed by [save] button in the main window, re-read the file to reflect new register settings.
[AKD4955-A] 2011/08 - 28 - 2. [data r/w]: data r/w dialog box click the [data r/w] button in the main window for data read/write dialog box. data write is available to specified address. figure 37.window of [data r/w] [address] box : input data address in hexadecimal numbers for data writing. [data] box : input data in hexadecimal numbers. [mask] box : input masks data in hexadecimal numbers. this is ?and? processed input data. [write] : writs the data generated from data and mask values to the address specified by ?address? box ( note 21 ). [read] : reads data from the address specified by ?address? box ( note 21 ). the result will be shown in the read data box in hexadecimal numbers. [close] : closes the dialog box and finishes the process. data writing can be cancelled by this button instead of executing a write command. note 21.the register map will be updated af ter executing [write] or [read] commands.
[AKD4955-A] 2011/08 - 29 - 3. [sequence]: sequence dialog box click [sequence] button to open register sequence setting dialog box. register sequence can be set in this dialog box. figure 38.window of [sequence] ~ sequence setting ~ set register sequence by following process bellow. 1. select a command use [select] pull-down box to choose commands. corresponding boxes will be valid. < select pull-down menu > no_use: not using this address register: register writing reg(mask): register writing (masked) interval: taking an interval stop: pausing the sequence end: finishing the sequence
[AKD4955-A] 2011/08 - 30 - 2. input sequence [address] : data address [data] : writing data [mask] : mask [data] box data is anded with [mask] box data. this is the actual writing data. when mask = 0x00, current setting is hold. when mask = 0xff, the 8bit data which is set in the [data] box is written. when mask =0x0f, lower 4bit data which is set in the [data] box is written. upper 4bit is hold to current setting. [interval] : interval time valid boxes for each process command are shown bellow. no_use : none register : [addre ss], [data], [interval] reg(mask) : [address], [data], [mask], [interval] interval : [interval] stop : none end : none ~ control buttons~ the function of control button is shown bellow. [start] : executes the sequence [help] : opens a help window [save] : saves sequence settings as a file. the file name is ?*.aks?. [open] : opens a sequence setting file ?*.aks?. [close] : closes the dialog box and finishes the process. ~ stop of the sequence~ when ?stop? is selected in the sequence, the process is paused and it starts again when [start] button is clicked restarting step number is shown in the ?start step? box. when finishing the process at the end of sequence, ?start step? will return to ?1?. the sequence can be started from any step by wr iting the step number to the ?start step? box. write ?1? to the ?start step? box and click [start] button, when restarting the process from the beginning.
[AKD4955-A] 2011/08 - 31 - 4. [sequence(file)]: sequence setting file dialog box click [sequence(file)] button to open sequence setting file dialog box. those files saved in the ?sequence setting dialog? can be applied in this dialog. figure 39.window of [sequence(file)] [open (left)] : opens a sequence setting file (*.aks). [start] : executes the sequen ce by the setting of selected file. [start all] : executing all sequence settings. selected files are executed in descending order. [help] : opens a help window. [save] : saves a sequence setting file assignment. the file name is ?*.mas?. [open(right)] : opens a saved sequ ence setting file assignment ?*. mas?. [close] : closes the dialog box and finishes the process. ~ operating suggestions ~ 1. those files saved by [save] button and opened by [open] button on the right of the dialog ?*.mas? should be stored in the same folder. 2. when ?stop? is selected in the sequence the proces s will be paused and a pop-up message will appear. click ?ok? to continue the process. figure 40.window of [sequence pause]
[AKD4955-A] 2011/08 - 32 - 5. [power management setting]: power management setting dialog box when [power management setting] button is clicked, the window as shown in figure 41 opens. refer to the datasheet for register settings of the ak4955. figure 41.window of [power management setting]
[AKD4955-A] 2011/08 - 33 - 6. [audio mode setting]: audio mode setting dialog box when [audio mode setting] button is clicked, the window as shown in figure 42 opens. refer to the datasheet for register settings of the ak4955. figure 42.window of [audio mode setting]
[AKD4955-A] 2011/08 - 34 - 7. [pll setting]: pll setting dialog box when [pll setting] button is clicked, the window as shown in figure 43 opens. refer to the datasheet for register settings of the ak4955. figure 43.window of [pll setting]
[AKD4955-A] 2011/08 - 35 - 8. [alc setting]: alc setting dialog box when [alc setting] button is clicked, the window as shown in figure 44 opens. refer to the datasheet for register settings of the ak4955. figure 44.window of [alc setting] [vol read]: when the button is pushed, reading ?vol? register is executed. gain: current volume is displayed in 1.5db step based on the reading result of the vol register value. data: the vol register value is displayed. (hex)
[AKD4955-A] 2011/08 - 36 - 9. [volume setting]: volume setting dialog box when [volume setting] button is clicked, the window as shown in figure 45 opens. refer to the datasheet for register settings of the ak4955. figure 45.window of [volume setting]
[AKD4955-A] 2011/08 - 37 - volume control by slider menu the volume can also be changed by writing a value in a dialog box. the slide bar is moved to the value that written in the dialog box. the up and down arrow keys to mouse or keyboard to adjust the settings. figure 46.volume slider slide bar is moved to the selected value the possible values are automatically selected.
[AKD4955-A] 2011/08 - 38 - 10. [video setting]: video setting dialog box when [video setting] button is clicked, the window as shown in figure 47 opens. refer to the datasheet for register settings of the ak4955. figure 47.window of [video setting]
[AKD4955-A] 2011/08 - 39 - 11. [beep setting]: beep setting dialog box when [beep setting] button is clicked, the window as shown in figure 48 opens. refer to the datasheet for register settings of the ak4955. figure 48.window of [beep setting]
[AKD4955-A] 2011/08 - 40 - 12. [dsp setting]: dsp setting dialog box when [dsp setting] button is clicked, the window as shown in figure 49 opens. refer to the datasheet for register settings of the ak4955. figure 49.window of [dsp setting]
[AKD4955-A] 2011/08 - 41 - 13. [digital filter]: filter setting dialog box when [digital filter] button is clicked, th e window as shown in figure 50 opens. refer to the datasheet for register settings of the ak4955. figure 50.window of [filter setting] [f response] : the filter characteristic dialog is displayed. [write] : the calculation of all filte rs and writing the coe fficient are executed. [register setting] : ?register setting for filter? dialog box is popped up. [close] : closing the dialog box and finish the process.
[AKD4955-A] 2011/08 - 42 - 13-1. parameter setting (1) please set a parameter of each filter. parameter function setting range sampling rate sampling frequency (fs) 7350hz fs 48000hz hpf cut off frequency high pa ss filter cut off frequency fs/10000 cut off frequency (0.497 * fs) lpf cut off frequency low pass filter cut off frequency fs/20 cut off frequency (0.497 * fs) fil3 cut off frequency fil3 cut off frequency fs/10000 cut off frequency (0.497 * fs) filter type the selection of filter type lpf or hpf gain gain -10 gain < 0 db eq0 pole frequency eq0 pole frequency fs/10000 cut off frequency (0.497 * fs) zero-point frequency eq0 zero-point frequency fs/10000 cut off frequency (0.497 * fs) gain gain -20 gain < +12 db gain2 gain2 0 / +12 / +24 db 5 band equalizer eq1-5 center frequency eq1-5 center frequency 0hz center frequency < (0.497 * fs) eq1-5 band width eq1-5 band width ( note 22 ) 1hz band width < (0.497 * fs) eq1-5 gain eq1-5 gain ( note 23 ) -1 gain < 3 table 7.parameter setting of [filter setting] note 22.a gain difference is a bandwidth of 3db from center frequency. note 23.when a gain is ?-1?, eq becomes a notch filter. (2) ?lpf enable?, ?hpf enab le?, ?hpfad enable?, ?fil 3 enable?, ?eq0 enable?, ?eq1?, ?eq2?, ?eq3?, ?eq4?, ?eq5? please set on/off of filter with a check button. when checked it, filter becomes on. when ?notch filter auto correction? is checked, perform automatic correction of the center frequen cy of the notch filter is executed. figure 51.filter on/off setting button
[AKD4955-A] 2011/08 - 43 - 13-2. [register setting]: register setting for filter dialog box a register set value is displayed when push a [register setting] button. when a value out of a setting range is set, error message is displayed, and a calculation of register setting is not carried out. figure 52.a register setting calculation result followings are the cases when a register set value is updated. (1) when [register setting] button was pushed. (2) when [frequency response] button was pushed. (3) when [update] button was pushed on a fr equency characteristic indication window. (4) when set on/off of a check button ?notch filter auto correction?
[AKD4955-A] 2011/08 - 44 - 13-3. [f response]: filter plot dialog box a frequency characteristic is displayed when push a [f response] button. then, a register set point is also updated. change frequency range, and indica tion of a frequency characteristic is updated when push a [update] button. figure 53. window of [f response] [frequency range] : the width of the frequency display is specified. [update] : it dr aws in the graph again. [gain/phase] : switch of ?gain/phase? display. [log view] : switch of ?linear/log? display. [close] : closing the dialog box and finish the process. ~ adjustment of vertical range ~ [y-axis ref] : display setting of center value. [vertical slider] : movement of vertical display. [horizontal slider] : adjustment of the horizontal display. (the left side reduces, and the right side expands. )
[AKD4955-A] 2011/08 - 45 - 13-4. 5-bandeq operation on filter plot screen when eq (1~5) is turning on, a green number is displayed on the filter plot dialog box. this number shows the setting of the center frequency and the gain of each eq. the number under the display is operated with the m ouse, and it is possible to set the filter characteristic on this screen. the center frequency and the gain setting are changed by moving the mouse while left-clicking. the setting of the bandwidth is changed by moving the mouse while right-clicking. figure 54.filter setting (left-clicking operation) figure 55.filter setting (right-clicking operation) after operating the mouse the value of the center frequency and the g ain is u p dated. the number is selected. the movement operation is done while lef t -clickin g . after operating the mouse the value of the bandwidth is updated.
[AKD4955-A] 2011/08 - 46 - 13-5. simulation of fil3 filter setting of stereo-mic [l-ch level]/[r-ch level] : the le vel of the mic input is input. [distance] : the distance betwee n the sound source and the mic is set. [angle] : the angle between the sound source and the mic is set. figure 56.simulation of fil3 filter
[AKD4955-A] 2011/08 - 47 - 13-6. about ?notch auto correct? if the gain of 5-band eq is set to ?- 1?, equalizer becomes a notch filter. when the center frequency of two or more notch filte rs is adjacent, the gap is generated in the center frequency. when ?notch auto correct? button is ch ecked, the center frequency of the notch filter is automatically corrected. the gain setting of the automa tic correction function is effective and only eq of ?-1? is effective. ( note 24 ) note 24.there is a possibility that the automatic compensa tion is not correctly done when the width of the center frequency is smaller than that of the bandwidth setting. setting of center frequency: 4400hz, 5000hz, 5400hz / bandwidth: 200hz (eq2~4) figure 57. ?notch auto correct? function is ?off? setting of center frequency: 4400hz, 5000hz, 5400hz / bandwidth: 200hz (eq2~4) figure 58. ?notch auto correct? function is ?on?
[AKD4955-A] 2011/08 - 48 - measurement result [measurement condition] ? measurement unit : audio precession system two cascade ? mclk : 12.2880mhz ? bick : 64fs ? fs : 48 khz ? bit : 24bit ? power supply : avdd = lvdd = svdd = 3.3v, dvdd = tvdd = 1.8v ? band width : 20 hz ~ 20 khz ? measurement mode : external slave mode ? temperature : room temperature [measurement result] 1. adc a). lin1/rin1 pins, mgain bits = ?+18db? parameter result lch / rch unit s/(n+d) (-1dbfs input) 81.0 / 81.5 db d-range (-60db input, a-weighted) 88.8 / 88.7 db s/n (no signal, a-weighted) 88.7 / 88.7 db b). lin2/rin2 pins, mgain bits = ?0db? parameter result lch / rch unit s/(n+d) (-1dbfs input) 81.7 / 82.2 db d-range (-60db input, a-weighted) 97.7 / 97.8 db s/n (no signal, a-weighted) 98.0 / 97.8 db 2. dac a). lout/rout pins, lvcm bits = ?01?, r l =10k ? parameter result lch / rch unit s/(n+d) (-3dbfs input) 87.5 / 87.6 db s/n (no signal, a-weighted) 92.6 / 92.5 db b). spp/spn pins, spkg bits = ?01?, r l =8 ? parameter result unit s/(n+d) (-0.5dbfs input) 80.5 db s/n (no signal, a-weighted) 96.7 db
[AKD4955-A] 2011/08 - 49 - plot data 1-a). adc [lin1/rin1 pins, mgain = ?+18db?] a km ak4955 s/(n+d) vs. input level [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" -130 -10 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 dbr -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b f s figure 59.s/(n+d) vs. input level a km ak4955 s/(n+d) vs. input frequency [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b f s figure 60.s/(n+d) vs. input frequency
[AKD4955-A] 2011/08 - 50 - a km ak4955 linearity [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" -110 +0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -110 +0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s t figure 61.linearity a km ak4955 frequency response [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -1.5 -0.5 -1.45 -1.4 -1.35 -1.3 -1.25 -1.2 -1.15 -1.1 -1.05 -1 -0.95 -0.9 -0.85 -0.8 -0.75 -0.7 -0.65 -0.6 -0.55 d b f s figure 62.frequency response
[AKD4955-A] 2011/08 - 51 - a km ak4955 crosstalk [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -70 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 d b tttttttttt tt t t tt t t t t t t tt tt tt ttttttttt t t tt tt t tt figure 63.crosstalk a km ak4955 fft (-1dbfs input) [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 64.fft (-1dbfs input)
[AKD4955-A] 2011/08 - 52 - a km ak4955 fft (-60dbfs input) [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 65.fft (-60dbfs input) a km ak4955 fft (no signal input) [ adc, lin1/rin1 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+18db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 66.fft (no signal input)
[AKD4955-A] 2011/08 - 53 - 1-b). adc [lin2/rin2 pins, mgain = ?0db?] a km ak4955 s/(n+d) vs. input level [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" -130 -10 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 dbr -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b f s figure 67.s/(n+d) vs. input level a km ak4955 s/(n+d) vs. input frequency [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b f s figure 68.s/(n+d) vs. input frequency
[AKD4955-A] 2011/08 - 54 - a km ak4955 linearity [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" -110 +0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -110 +0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 69.linearity a km ak4955 frequency response [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -1.5 -0.5 -1.45 -1.4 -1.35 -1.3 -1.25 -1.2 -1.15 -1.1 -1.05 -1 -0.95 -0.9 -0.85 -0.8 -0.75 -0.7 -0.65 -0.6 -0.55 d b f s figure 70.frequency response
[AKD4955-A] 2011/08 - 55 - a km ak4955 crosstalk [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -70 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 d b ttttt t tttt figure 71.crosstalk a km ak4955 fft (-1dbfs input) [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 72.fft (-1dbfs input)
[AKD4955-A] 2011/08 - 56 - a km ak4955 fft (-60dbfs input) [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 73.fft (-60dbfs input) a km ak4955 fft (no signal input) [ adc, lin2/rin2 ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, mgain="+0db" 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 74.fft (no signal input)
[AKD4955-A] 2011/08 - 57 - 2-a). dac [lout/rout pins, lvcm(1-0) bits = ?01?] a km ak4955 thd+n vs. input level [ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm -120 -10 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 dbfs -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b r a figure 75.s/(n+d) vs. input level a km ak4955 thd+n vs. input frequency [ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b r a figure 76.s/(n+d) vs. input frequency
[AKD4955-A] 2011/08 - 58 - a km ak4955 linearity [ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm -110 +0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -110 +0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 77.linearity a km ak4955 frequency response [ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -3.5 -2.5 -3.4 -3.3 -3.2 -3.1 -3 -2.9 -2.8 -2.7 -2.6 d b r a figure 78.frequency response (pin direct)
[AKD4955-A] 2011/08 - 59 - a km ak4955 crosstalk [ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -70 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 d b tttttttttt tt ttttttttt t figure 79.crosstalk a km ak4955 fft (-3dbfs input)[ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 80.fft (-3dbfs input)
[AKD4955-A] 2011/08 - 60 - a km ak4955 fft (-60dbfs input)[ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 81.fft (-60dbfs input) a km ak4955 fft (no signal input)[ dac, lineout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, lvcmbit="01", rl=10kohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 82.fft (no signal input)
[AKD4955-A] 2011/08 - 61 - 2-b). dac [spp/spn pins, spkg(1-0) bits = ?01?] a km ak4955 thd+n vs. input level [ dac, spkout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, spkgbit="01", rl=8ohm -120 -10 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 dbfs -100 -70 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 d b r a figure 83.s/(n+d) vs. input level a km ak4955 thd+n vs. input frequency [ dac, spkout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, spkgbit="01", rl=8ohm -100 -60 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 84.s/(n+d) vs. input frequency
[AKD4955-A] 2011/08 - 62 - a km ak4955 linearity [ dac, spkout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, spkgbit="01", rl=8ohm -110 +0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 85.linearity a km ak4955 frequency response [ dac, spkout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, spkgbit="01", rl=8ohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -1 +0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 d b r a figure 86.frequency response
[AKD4955-A] 2011/08 - 63 - a km ak4955 fft (-0.5dbfs input)[ dac, spkout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, spkgbit="01", rl=8ohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 87.fft (-0.5dbfs input) a km ak4955 fft (-60dbfs input)[ dac, spkout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, spkgbit="01", rl=8ohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 88.fft (-60dbfs input)
[AKD4955-A] 2011/08 - 64 - a km ak4955 fft (no signal input)[ dac, spkout ] avdd=lvdd=svdd=3.3v, dvdd=tvdd=1.8v, fs=48khz, external slave mode, spkgbit="01", rl=8ohm 20 20k 50 100 200 500 1k 2k 5k 10k hz -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 89.fft (no signal input)
[AKD4955-A] 2011/08 - 65 - 3. video plot data [measurement condition] ? measurement unit : tektronix vm700t video measurement set ? power supply : avdd = lvdd = svdd = 3.3v, dvdd = tvdd = 1.8v ? temperature : room temperature ? input level : 1.0vpp input ? vg bits : ?00? (+6db) ? s/n ? input signal : 0% flat field ? measurement frequency : 100kh 6mhz figure 90.noise spectrum
[AKD4955-A] 2011/08 - 66 - ? dc ? input signal : field square wave figure 91.field time distortion
[AKD4955-A] 2011/08 - 67 - ? vector ? input signal : 75% color bar figure 92.vector
[AKD4955-A] 2011/08 - 68 - revision history important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustra te the operation and application exam ples of the semiconductor products. you are fully responsible for the incorporation of these ex ternal circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these inform ation herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet ve ry high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. date (yy/mm/dd) manual revision board revision reason page contents 11/08/24 km104703 3 first edition -
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vss1 vss1 title size document number rev date: sheet of AKD4955-A-36csp-sub 1 AKD4955-A a2 11 monday, november 29, 2010 title size document number rev date: sheet of AKD4955-A-36csp-sub 1 AKD4955-A a2 11 monday, november 29, 2010 title size document number rev date: sheet of AKD4955-A-36csp-sub 1 AKD4955-A a2 11 monday, november 29, 2010 lin1 rin2 lin2 rin1 cad0 cdtio rin1 digital mic dmclk lin1 dmdat csn sda tp108 lin2 tp108 lin2 tp115 vss3 tp115 vss3 c115 0.1u c115 0.1u tp136 csn tp136 csn r105 (open) r105 (open) tp116 bick tp116 bick tp111 mpwr tp111 mpwr tp126 vss1a tp126 vss1a tp107 lout tp107 lout tp124 min tp124 min tp125 sdto tp125 sdto tp109 rin2 tp109 rin2 tp130 vin tp130 vin jp103 cdtio/cad0 jp103 cdtio/cad0 c105 1u c105 1u tp121 vss1b tp121 vss1b tp131 vout tp131 vout cn7 cn7 1 + c118 10u + c118 10u tp113 svdd tp113 svdd tp120 vss2 tp120 vss2 jp102 lin1-sel jp102 lin1-sel r119 51 r119 51 c102 1u c102 1u c116 2.2u c116 2.2u c110 0.1u c110 0.1u c119 (open) c119 (open) r122 75 r122 75 r104 (open) r104 (open) cn5 cn5 1 2 tp106 sdti tp106 sdti r103 0 r103 0 tp118 dvdd tp118 dvdd c109 0.1u c109 0.1u r113 51 r113 51 tp135 cclk/scl tp135 cclk/scl tp127 avdd tp127 avdd r100 0 r100 0 r102 0 r102 0 r118 100k r118 100k tp137 i2c tp137 i2c r111 2.2k r111 2.2k tp105 rout tp105 rout + c107 10u + c107 10u r123 75 r123 75 tp114 lrck tp114 lrck tp110 lin1 tp110 lin1 c112 0.1u c112 0.1u jp104 csn/sda jp104 csn/sda tp128 mcko tp128 mcko tp112 spn tp112 spn r120 0 r120 0 tp123 regfil tp123 regfil r101 0 r101 0 + c108 10u + c108 10u cn3 64pin cn3 64pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 u100 ak4955ecb u100 ak4955ecb cclk/scl a1 cdtio/cad0 b2 csn/sda b1 pdn c1 vin d1 vss1 e1 pvee f1 vout c2 i2c d2 mcko a2 sdto a3 vss2 a4 bick a5 mcki a6 dvdd b4 tvdd b3 sdti b6 lrck b5 rout c5 rin1 c6 lin1 d6 min c3 vss1 f2 avdd e2 vcom f4 svdd e6 mpwr e3 vss1 e4 lin2 d3 lout c4 rin2 d4 regfil f3 lvdd d5 spp e5 spn f6 vss3 f5 tp101 dmdat tp101 dmdat tp117 lvdd tp117 lvdd tp122 tvdd tp122 tvdd jp100 mpwr-sel jp100 mpwr-sel r106 0 r106 0 c101 (short) c101 (short) tp132 pdn tp132 pdn cn6 cn6 1 c121 0.1u c121 0.1u c104 1u c104 1u cn1 64pin cn1 64pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r115 100k r115 100k r116 51 r116 51 tp100 dmclk tp100 dmclk tp133 pvee tp133 pvee c103 1u c103 1u r117 100k r117 100k tp102 spp tp102 spp + c111 10u + c111 10u c117 0.1u c117 0.1u c100 (short) c100 (short) r108 2.2k r108 2.2k jp101 rin1-sel jp101 rin1-sel r110 2.2k r110 2.2k tp104 mcki tp104 mcki tp129 cdtio/sda tp129 cdtio/sda tp138 vss1c tp138 vss1c r107 51 r107 51 r114 51 r114 51 c120 2.2u c120 2.2u c106 0.1u c106 0.1u tp119 vcom tp119 vcom cn4 64pin cn4 64pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 cn2 64pin cn2 64pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c122 (open) c122 (open) tp103 rin1 tp103 rin1 tp134 cad0 tp134 cad0 r109 2.2k r109 2.2k r121 0 r121 0 + c113 2.2u + c113 2.2u 3 - 69 -
a a b b c c d d e e e e d d c c b b a a lin1 rin1 lin2 rin2 lout rout min spn spp svdd lvdd avdd ak4955-sdti ak4955-mcki ak4955-lrck ak4955-bick dvdd tvdd cdtio/sda ak4955-sdto ak4955-mcko vout cad0 cclk/scl csn i2c pdn vin title size document number rev date: sheet of under the sub-board 1 AKD4955-A a2 16 monday, november 29, 2010 title size document number rev date: sheet of under the sub-board 1 AKD4955-A a2 16 monday, november 29, 2010 title size document number rev date: sheet of under the sub-board 1 AKD4955-A a2 16 monday, november 29, 2010 cn4 64pin cn4 64pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 cn2 64pin cn2 64pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cn3 64pin cn3 64pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cn1 64pin cn1 64pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3 - 70 -
a a b b c c d d e e e e d d c c b b a a min vout lout rout spp spn vin lin2 lin1 rin2 rin1 title size document number rev date: sheet of input/output 1 AKD4955-A a3 26 monday, november 29, 2010 title size document number rev date: sheet of input/output 1 AKD4955-A a3 26 monday, november 29, 2010 title size document number rev date: sheet of input/output 1 AKD4955-A a3 26 monday, november 29, 2010 ext int l1-mini l1-bnc l2-bnc r1-mini r1-bnc l2-mini r2-mini r2-bnc tp44 min tp44 min j3 lin j3 lin 1 2 3 4 5 jp9 spk-gnd jp9 spk-gnd j9 spk-out j9 spk-out 5 2 1 j2 vin j2 vin 1 2 3 4 5 r25 (short) r25 (short) c31 (open) c31 (open) c27 (open) c27 (open) + c29 1u + c29 1u j8 min j8 min 1 2 3 4 5 + c25 (short) + c25 (short) r63 16 r63 16 jp6 lin-sel jp6 lin-sel c26 (open) c26 (open) j4 vout j4 vout 1 2 3 4 5 + c24 (short) + c24 (short) tp41 mini-rch tp41 mini-rch r30 33k r30 33k r26 220 r26 220 r31 33k r31 33k j5 rin j5 rin 1 2 3 4 5 j6 lout j6 lout 1 2 3 4 5 tp40 mini-lch tp40 mini-lch jp7 rin-sel jp7 rin-sel c32 (open) c32 (open) r27 20k r27 20k j1 ain j1 ain 5 2 1 r29 20k r29 20k + c28 1u + c28 1u r32 16 r32 16 jp8 min-sel jp8 min-sel tp43 bnc-rch tp43 bnc-rch + c30 1u + c30 1u r28 220 r28 220 j7 rout j7 rout 1 2 3 4 5 r24 (open) r24 (open) tp42 bnc-lch tp42 bnc-lch 3 - 71 -
a a b b c c d d e e e e d d c c b b a a d3v ocks1 d3v d3v d3v ocks1 d3v dio-pdn mcko daux dir-bick dir-sdto dir-lrck dir-mcki int0 d3v title size document number rev date: sheet of dir/dit 1 AKD4955-A a3 36 monday, november 29, 2010 title size document number rev date: sheet of dir/dit 1 AKD4955-A a3 36 monday, november 29, 2010 title size document number rev date: sheet of dir/dit 1 AKD4955-A a3 36 monday, november 29, 2010 dif2 dif1 dif0 ocks1 h l mcko xtl tp45 rx tp45 rx r34 10k r34 10k c44 0.1u c44 0.1u l1 47u l1 47u 1 2 rp1 47k rp1 47k 5 4 3 2 1 port2 totx port2 totx gnd 1 vcc 2 in 3 u2 ak4118a u2 ak4118a ips0/rx4 1 nc 2 dif0/rx5 3 test2 4 dif1/rx6 5 vss1 6 dif2/rx7 7 ips1/iic 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 nc/gp1 14 tx0/gp2 15 tx1/gp3 16 bout/gp4 17 cout/gp5 18 uout/gp6 19 vout/gp7 20 dvdd 21 vss2 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0/cdto/cad1 32 cm1/cdti/sda 33 ocks1/cclk/scl 34 ocks0/csn/cad0 35 int0 36 avdd 38 r 39 vcom 40 vss3 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 vss4 47 rx3 48 vin/gp0 12 lrck 24 sdto 25 int1 37 sw1 sw1 1 2 3 4 8 7 6 5 + c34 10u + c34 10u c33 0.1u c33 0.1u + c43 10u + c43 10u jp10 xti-sel jp10 xti-sel r33 51 r33 51 c41 0.1u c41 0.1u + c35 10u + c35 10u x1 12.288mhz x1 12.288mhz 1 2 c38 5p c38 5p c36 0.1u c36 0.1u + c42 10u + c42 10u c40 0.1u c40 0.1u port1 torx port1 torx out 1 vcc 3 gnd 2 c39 5p c39 5p tp46 tx tp46 tx c37 0.47u c37 0.47u 3 - 72 -
a a b b c c d d e e e e d d c c b b a a dir-bick d3v d3v lvc d3v dio-pdn int0 dir-lrck pdn lvc lvc ak4955-bick ak4955-lrck m/s d3v ak4955-sdto ak4955-mcko ak4955-sdti ak4955-mcki d3v lvc dir-sdto daux mcko dir-mcki cad0 m/s lvc i2c title size document number rev date: sheet of clock & sw 1 AKD4955-A a3 46 monday, november 29, 2010 title size document number rev date: sheet of clock & sw 1 AKD4955-A a3 46 monday, november 29, 2010 title size document number rev date: sheet of clock & sw 1 AKD4955-A a3 46 monday, november 29, 2010 dir 4040-64fs 4040-32fs ext gnd 10pin h l h l thr inv dir 4040 adc dir mcko mcki mclk bick lrck sdti sdto 10pin dir 10pin 10pin mcko mcki i2c cad0 m/s h l u5 74hc14 u5 74hc14 gnd 7 1a 1 3a 5 5a 11 5y 10 3y 6 1y 2 2y 4 4y 8 6y 12 6a 13 4a 9 2a 3 vcc 14 sw4 sw4 1 2 3 6 5 4 sw2 dio-pdn sw2 dio-pdn 2 1 3 jp13 lrck-sel jp13 lrck-sel jp18 ext jp18 ext c49 0.1u c49 0.1u rp2 47k rp2 47k 3 2 1 c53 0.1u c53 0.1u jp16 mcki-sel jp16 mcki-sel r36 1k r36 1k c51 0.1u c51 0.1u u4 74avc4t245 u4 74avc4t245 1a1 4 1a2 5 2a2 7 1oe 15 1b1 13 1b2 12 2b1 11 2b2 10 gnd 9 2a1 6 1dir 2 vccb 16 vcca 1 gnd 8 2dir 3 2oe 14 jp14 mckio jp14 mckio c52 0.1u c52 0.1u c47 0.1u c47 0.1u jp11 bick-sel jp11 bick-sel le1 int0 le1 int0 2 1 r37 10k r37 10k jp15 sdti-sel jp15 sdti-sel jp12 bick-phase jp12 bick-phase r38 51 r38 51 d2 hsu119 d2 hsu119 k a j10 ext j10 ext 1 2 3 4 5 c45 0.1u c45 0.1u u3 74hc4040 u3 74hc4040 clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 vd 16 dgnd 8 c48 0.1u c48 0.1u u7 74hc14 u7 74hc14 gnd 7 1a 1 3a 5 5a 11 5y 10 3y 6 1y 2 2y 4 4y 8 6y 12 6a 13 4a 9 2a 3 vcc 14 c46 0.1u c46 0.1u ::|:?:?:? dsp ::|:?:?:? dsp 1 3 5 7 9 10 8 6 4 2 jp17 4040-sel jp17 4040-sel u6 74avc4t245 u6 74avc4t245 1a1 4 1a2 5 2a2 7 1oe 15 1b1 13 1b2 12 2b1 11 2b2 10 gnd 9 2a1 6 1dir 2 vccb 16 vcca 1 gnd 8 2dir 3 2oe 14 sw3 pdn sw3 pdn 2 1 3 d1 hsu119 d1 hsu119 k a c50 0.1u c50 0.1u r35 10k r35 10k 3 - 73 -
a a b b c c d d e e e e d d c c b b a a vss2 vss2 d3v d3v lvc csn cclk/scl cdtio/sda lvc d3v title size document number rev date: sheet of up-i/f 1 AKD4955-A a3 56 monday, november 29, 2010 title size document number rev date: sheet of up-i/f 1 AKD4955-A a3 56 monday, november 29, 2010 title size document number rev date: sheet of up-i/f 1 AKD4955-A a3 56 monday, november 29, 2010 csn cclk/scl cdti/sda cdto/sda(ack) 10pin 10pin 10pin 10pin usb usb usb usb silk-screen(p1) 1:vdd 2:mclr 3:pgd 4:pgc 5:gnd csn cclk/scl cdto/sda(ack) cdti/sda xti xto usb-rst csn cclk/scl cdti/sda cdto/sda(ack) t1 5v => 3.3v tk73633ame t1 5v => 3.3v tk73633ame nc 1 vout 2 pcl 3 gnd 4 nc 8 vin 7 nc 5 vcont 6 x2 20mhz x2 20mhz tp53 rd6 tp53 rd6 + c55 10u + c55 10u c54 2.2u c54 2.2u c58 0.1u c58 0.1u tp51 rd4 tp51 rd4 r51 51 r51 51 r53 51 r53 51 r44 470 r44 470 r54 0 r54 0 c63 22p c63 22p c64 22p c64 22p u11 74lvc07 u11 74lvc07 1a 1 2a 3 3a 5 4a 9 5a 11 6a 13 vcc 14 gnd 7 1y 2 2y 4 3y 6 4y 8 5y 10 6y 12 r48 1k r48 1k r52 51 r52 51 tp49 rd2 tp49 rd2 r50 51 r50 51 c62 0.1u c62 0.1u tp54 rd7 tp54 rd7 r49 100 r49 100 r46 470 r46 470 r47 100k r47 100k r43 10k r43 10k tp47 rd0 tp47 rd0 jp28 ctrl-sel jp28 ctrl-sel r39 4.7k r39 4.7k tp52 rd5 tp52 rd5 jp29 pic jp29 pic 1 2 3 4 5 u8 74avc4t245 u8 74avc4t245 1a1 4 1a2 5 2a2 7 1oe 15 1b1 13 1b2 12 2b1 11 2b2 10 gnd 9 2a1 6 1dir 2 vccb 16 vcca 1 gnd 8 2dir 3 2oe 14 + c56 10u + c56 10u c57 0.1u c57 0.1u u10 usb(b type) u10 usb(b type) vusb 1 d- 2 d+ 3 gnd 4 pic18f4550 tqfp 44-pin u9 pic18f4550 pic18f4550 tqfp 44-pin u9 pic18f4550 rc7/rx/dt/sdo 1 rd4/spp4 2 rd5/spp5/p1b 3 rd6/spp6/p1c 4 rd7/spp7/p1d 5 vss0 6 vdd0 7 rb0/an12/int0/flt0/sdi/sda 8 rb1/an10/int1/sck/scl 9 rb2/an8/int2/vmo 10 rb3/an9/cpp2/vpo 11 nc/icck/icpgc 12 nc/icdt/icpgd 13 rb4/an11/kbi0/csspp 14 rb5/kbi1/pgm 15 rb6/kbi2/pgc 16 rb7/kbi3/pgd 17 mclr_n/vpp/re3 18 ra0/an0 19 ra1/an1 20 ra2/an2/vref-/cvref 21 ra3/an3/vref+ 22 ra4/t0cki/c1out/rcv 23 ra5/an4/ss_n/hlvdin/c2out 24 re0/an5/ck1spp 25 re1/an6/ck2spp 26 re2/an7/oespp 27 vdd1 28 vss1 29 osc1/clki 30 osc2/clko/ra6 31 rc0/t1oso/t13cki 32 nc/icrst_n/icvpp 33 nc/icports 34 rc1/t1osi/ccp2/uoe_n 35 rc2/ccp1/p1a 36 vusb 37 rd0/spp0 38 rd1/spp1 39 rd2/spp2 40 rd3/spp3 41 rc4/d-/vm 42 rc5/d+/vp 43 rc6/tx/ck 44 port4 10pin-ctrl port4 10pin-ctrl 1 3 5 7 9 10 8 6 4 2 r45 470 r45 470 c61 0.1u c61 0.1u tp50 rd3 tp50 rd3 c65 470n c65 470n r40 10k r40 10k c60 0.1u c60 0.1u r41 10k r41 10k c66 0.1u c66 0.1u r42 10k r42 10k c59 1u c59 1u tp48 rd1 tp48 rd1 r55 0 r55 0 3 - 74 -
a a b b c c d d e e e e d d c c b b a a avdd lvdd svdd d3v dvdd tvdd lvc title size document number rev date: sheet of power supply 1 AKD4955-A a3 66 monday, november 29, 2010 title size document number rev date: sheet of power supply 1 AKD4955-A a3 66 monday, november 29, 2010 title size document number rev date: sheet of power supply 1 AKD4955-A a3 66 monday, november 29, 2010 reg avdd reg lvdd reg svdd reg d3v reg dvdd reg lvc + c67 47u + c67 47u tp58 gnd4 tp58 gnd4 + c72 47u + c72 47u r61 (short) r61 (short) + c75 47u + c75 47u + c73 47u + c73 47u r60 (short) r60 (short) j18 lvc j18 lvc 1 j19 svdd j19 svdd 1 tp56 gnd2 tp56 gnd2 c69 2.2u c69 2.2u jp25 svdd-sel jp25 svdd-sel j20 d3v j20 d3v 1 tp55 gnd1 tp55 gnd1 jp21 dvdd-sel jp21 dvdd-sel r59 (short) r59 (short) j14 avdd j14 avdd 1 j17 lvdd j17 lvdd 1 jp23 lvdd-sel jp23 lvdd-sel j15 dvdd j15 dvdd 1 r58 (short) r58 (short) j11 +5v j11 +5v 1 jp19 gnd jp19 gnd jp20 avdd-sel jp20 avdd-sel r62 (short) r62 (short) c68 1u c68 1u tp57 gnd3 tp57 gnd3 c70 1u c70 1u j13 agnd j13 agnd 1 t3 5v => 1.8v tk73618ame t3 5v => 1.8v tk73618ame nc 1 vout 2 pcl 3 gnd 4 nc 8 vin 7 nc 5 vcont 6 + c76 47u + c76 47u + c77 47u + c77 47u r57 (short) r57 (short) t2 5v => 3.3v tk73633ame t2 5v => 3.3v tk73633ame nc 1 vout 2 pcl 3 gnd 4 nc 8 vin 7 nc 5 vcont 6 jp26 d3v-sel jp26 d3v-sel jp24 lvc-sel jp24 lvc-sel c71 2.2u c71 2.2u j12 dgnd j12 dgnd 1 + c78 47u + c78 47u r56 (short) r56 (short) 3 - 75 -
AKD4955-A rev.3 y
?
??3??
$ 3 - 76 -
AKD4955-A rev.3 y
r >?3??
$ - 77 -
AKD4955-A rev.3 y
?
?????
$ - 78 -
AKD4955-A rev.3 y o
l2 ???
$ - 79 -
AKD4955-A rev.3 y o
l3 ???
$ - 80 -
AKD4955-A rev.3 y o
l4 ???
$ - 81 -
AKD4955-A rev.3 y o
l5 ???
$ - 82 -
AKD4955-A rev.3 y
r >????
$ - 83 -
AKD4955-A rev.3
?
??3??
$ 3 - 84 -
AKD4955-A rev.3
r >?3??
$ - 85 -
AKD4955-A rev.3
?
?????
$ - 86 -
AKD4955-A rev.3 o
l2 ???
$ - 87 -
AKD4955-A rev.3 o
l3 ???
$ - 88 -
AKD4955-A rev.3
r >????
$ - 89 -
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